Various semiconductor devices are manufactured on semiconductor substrates, e.g., a field effect transistor, a floating gate FLASH memory cell, a SONOS (Silicon/Oxide/Nitride/Oxide/Silicon) type FLASH memory device or the like. Such devices continue to be scaled in order to increase the number of devices formed on a chip that forms an integrated circuit (IC). Given the continuing trend towards miniaturization and increased integration of devices on an integrated circuit chip, the capability to manufacture the substructures precisely and with high quality is of increasing importance.
A vertical stack of non-conductive material and conductive material formed sequentially over a semiconductor substrate characterizes field effect transistors. Specifically, the vertical stack includes a gate electrode formed over a gate dielectric. The gate electrode defines a channel within a doped region interposed between a source and a drain formed in the semiconductor substrate.
Subsequently, floating gate FLASH memory types of EEPROMs (electrically erasable programmable read-only memory) have been produced. EEPROMs employ a FLASH memory cell formed over a semiconductor substrate. The FLASH memory cell is characterized by a vertical stack of a tunnel oxide, a first polysilicon layer (charge trapping conducting layer, i.e., a floating gate) over the tunnel oxide, an ONO (oxide-nitride-oxide) intergate dielectric over the first polysilicon layer, and a second polysilicon layer (i.e., a control gate) over the ONO intergate dielectric. The floating gate defines a channel within a doped region interposed between two bitlines formed in the semiconductor substrate. The bitlines, as described above, are doped regions that may act as either a source or a drain.
More recently, SONOS (Silicon/Oxide/Nitride/Oxide/Silicon) type FLASH memory devices have been produced. The SONOS type FLASH memory cells are also characterized by a vertical stack formed over a semiconductor substrate. The SONOS vertical stack includes a charge trapping non-conducting dielectric layer, typically a silicon nitride layer, sandwiched between two silicon dioxide layers (insulating layers), i.e., a lower silicon dioxide layer and an upper silicon dioxide layer.
The charge trapping non-conducting dielectric layer functions as an electrical charge trapping medium. The charge trapping non-conducting dielectric layer may have two separated and separately chargeable areas, i.e., a left bit and a right bit. Each area defines one bit.
A conducting gate layer, i.e., a control gate, is formed over the upper silicon dioxide layer. The SONOS type FLASH memory cell has a lightly doped region (the channel) between two bitlines, i.e., a left bitline and a right bitline (it should be understood by those having ordinary skill in the art that the terms source and drain could be used interchangeably with the term bitlines in this context). The left bitline or the right bitline may act as either a source or a drain. An electrical charge may be trapped locally, i.e., in either the left bit or the right bit, near whichever bitline is used-as a drain.
The devices are formed using known semiconductor processing techniques to deposit one or more layers of dielectric material and conductive material sequentially based on the device to be made. Next, the one or more layers are patterned and etched to form the gate stacks described above. The etching process is typically multiple etching steps. An etchant species is selected for a particular etch step that is selective between the material to be etched and the material which is to remain relatively unetched.
For illustrative purposes, the process for forming an EEPROM memory cell is described as follows: forming an ONO dielectric over a semiconductor substrate, depositing polysilicon over the ONO dielectric, and patterning and etching the polysilicon to form gate electrodes or wordlines.
The patterning and etching of the polysilicon is usually accomplished by depositing and patterning a photosensitive layer over the polysilicon to form a lithographic image in the photosensitive layer, i.e., a photosensitive mask. Next, portions of polysilicon exposed by apertures in the photosensitive mask are etched/removed. Then, the photosensitive mask is removed to expose the patterned polysilicon. Thus, polysilicon wordlines/gate electrodes are formed over the ONO dielectric.
Unfortunately, as manufacturers scale down the device dimensions to increase the performance and reduce the cost of manufacture, the scaling down of devices has led to the development of several undesirable results during the processing of the semiconductor devices. For example, as the dimensions of the horizontal and vertical lines and the spaces therebetween of an IC are reduced, the ability to produce the horizontal and vertical lines and the spaces therebetween with precise dimensions is limited. As is understood by those having ordinary skill in the art, the length dimensions of the horizontal and vertical lines of a mask are reduced in the lithographic image produced in the photosensitive layer and subsequently in a device layer to be patterned due to many variables, e.g., the illumination conditions at the line ends, the quality of the photosensitive mask produced, variations in the thickness of the photosensitive mask, the etchant species used or a combination thereof. In cases where wafer area is not a limiting factor, the length of the vertical and horizontal lines can be extended on the mask to account for line end pull back. For example, to produce a 100 nm line in a device layer, a 100 nm line on the mask would be extended 15 nm on each end (30 nm total) to account for a 15 nm reduction at each line end. However, a line may not be extended when there are horizontal and vertical lines in close proximity and an extension of one line would cause the extended line to intersect another line. Accordingly, a device produced from such a mask may be inoperative or the operation of such device may be significantly degraded.
In an attempt to overcome this problem, mask designers design masks to prevent the intersection of an extended line with another line. That is, a mask is produced with a space between the horizontal and the vertical lines. However, due to line end pull back, the space increases between the horizontal and the vertical lines in the device layer resulting in a space greater than desired. As a result, a significant amount of wafer area will be wasted and the number of devices that can be produced from the wafer significantly decreased.
Therefore, there exists a strong need in the art for a method which produces semiconductor devices that reduce the effects due to line end pull back. There is also a need to produce precise features in a layer to be patterned. Further, there is a need to produce the features with a precise space therebetween. Further still, there is a need to produce precise features with dimensions that cannot be achieved using lithography processes alone. Such an invention would allow the further scaling of semiconductor devices and increase performance.